On-chip tap-delay measurements for a digital delay-line used in high-speed inter-chip data communications

Abstract

During the last few years, new synchronization techniques to send data between ICs at increasingly high data-rates have been developed. Some of them rely on digital delay lines. The timing accuracy of the delay lines is crucial for good functionality of the synchronization mechanism. This paper presents a strategy to measure the tap-delays of a digital delay-line, using the well-known oscillation technique. The occurring measurement error for the presented technique has been calculated. Towards the end of the paper, a new delay-line scheme is shown. The tap-delay, measurement becomes much more accurate for this delay-line than for a standard delay-line.