Density aware interconnect parasitic estimation for mixed signal design

Abstract

With the current advancement of the design technology process, the contribution of interconnects parasitic to critical path delays has become crucial in determining the overall chip performance. A reliable parasitic estimation tool can help in assisting the design decisions as well as enabling a more precise synthesis; minimizing the tedious repetitive design cycles of placement and routing process. Experiments show that different interconnects estimation algorithms produce different parasitic RC values. To achieve an accurate parasitic capacitance prediction, several approaches were investigated and a new methodology of estimation is proposed. The new algorithm performs estimation prior to layout. It modifies the conventional estimation methodology by taking into account the layout density specification for a more precise interconnects parasitic capacitance estimation. The algorithm is divided into two stages; the pre-layout routing estimation and the generation of interconnect parasitic values. The layout density specification is brought into consideration on the second phase of the estimation process. The accuracy of the approximation is determined by comparing the estimated results with the actual post-layout data. The final outcome is positive, showing a good correlation between the pre-layout and post-layout measures; varying within 10 percent of the final extracted values.