Fast and slow border traps in MOS devices

Abstract

Convergent lines of evidence are reviewed which show that near-interfacial oxide traps (border traps) that exchange charge with the Si can strongly affect the performance, radiation response, and long-term reliability of MOS devices. Observable effects of border traps include capacitance-voltage (C-V) hysteresis, enhanced 1/f noise, compensation of trapped holes, and increased thermally stimulated current in MOS capacitors. Effects of faster (switching times between /spl sim/10/sup -6/ s and /spl sim/1 s) and slower (switching times greater than /spl sim/1 s) border traps have been resolved via a dual-transistor technique. In conjunction with studies of MOS electrical response, electron paramagnetic resonance and spin dependent recombination studies suggest that E' defects (trivalent Si centers in SiO/sub 2/ associated with O vacancies) can function as border traps in MOS devices exposed to ionizing radiation or high-field stress. Hydrogen-related centers may also be border traps.