ASIC leakage, performance and area tradeoff analysis

Abstract

Power Optimization is essential part of early design planning stage besides performance. The blooming of mobile applications era further drive the need for power reduction in SOC design. Though SOC designers can opt for commercial EDA tools for concurrent timing, power, noise optimization, a thorough leakage, performance, area trade off analysis is required during design definition phase to ensure optimum performance, area, power and cost. The intend of this paper is to share some of the prior art leakage power trade off analysis in early SOC design planning phase.