Emulation of double gate transistor in ultra-thin body with thin buried oxide SOI MOSFETs

Abstract

Thin body Silicon-on-Insulator (SOI) devices are promising technology for extending the device scalability as projected in ITRS, thanks to immunity to short channel effects. Further improvement can be achieved when the device incorporated with thin buried oxide (BOX) since it allows suppression of fringing electric fields through the BOX thus improving front-gate-to-channel controllability and reducing DIBL. Thin BOX is also suitable for emulation of double-gate (implementing back-gate biasing) schemes used for tuning device characteristics. Thus, in this paper, from the advantages of double gate transistor, we investigate by using ATLAS 2D-simulations the emulation of double gate transistor with bottom contact (underneath the substrate) and top contact (from the top through the silicon and BOX) for both digital and analog/RF figures of merit in ultra-thin body and thin buried oxide (UTBB) SOI MOSFETs. Improvement in performance simply can be achieved with such configurations.