{"title":"A 30 to 44 GHz divide-by-2, quadrature, direct injection locked frequency divider for sliding-IF 60 GHz transceivers","authors":"H. M. Cheema, R. Mahmoudi, A. V. van Roermund","doi":"10.1109/SMIC.2010.5422946","DOIUrl":null,"url":null,"abstract":"This paper presents a wideband 40 GHz divide-by-2 quadrature injection locked frequency divider (Q-ILFD) as an enabling component for sliding-IF 60 GHz transceivers. The design incorporates direct injection topology and input power matching using interconnect inductances to enhance injection efficiency. This results in an excellent input sensitivity and a wide locking range. Fabricated in a 65nm bulk CMOS technology, the divider operates from 30.3 to 44 GHz (37% locking range) while consuming 9mW from a 1.2V supply. The measured phase noise is −131 dBc/Hz at 1-MHz offset whereas the phase error between I-Q outputs is less than 1.44°.","PeriodicalId":404957,"journal":{"name":"2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMIC.2010.5422946","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12
Abstract
This paper presents a wideband 40 GHz divide-by-2 quadrature injection locked frequency divider (Q-ILFD) as an enabling component for sliding-IF 60 GHz transceivers. The design incorporates direct injection topology and input power matching using interconnect inductances to enhance injection efficiency. This results in an excellent input sensitivity and a wide locking range. Fabricated in a 65nm bulk CMOS technology, the divider operates from 30.3 to 44 GHz (37% locking range) while consuming 9mW from a 1.2V supply. The measured phase noise is −131 dBc/Hz at 1-MHz offset whereas the phase error between I-Q outputs is less than 1.44°.