PROGRAMMING FOR PARALLEL PATTERN GENERATORS

M. Kanzaki, M. Ishida
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引用次数: 1

Abstract

This paper a!escribes the design and use of parallel pattern generaliors in a Memory Test System to achieve high speed testing of memory integrated circuitdr. Both the hardware design and the software design of this subsystem is described. This Test System has been put into practical use and has resulted in the evaluation and testing of very high speed memories in a signi,ficantly shorter time than with conventional systems.
并行模式生成器编程
这篇论文!描述了在存储器测试系统中并行模式通用器的设计和使用,以实现存储器集成电路的高速测试。介绍了该子系统的硬件设计和软件设计。该测试系统已投入实际使用,与传统系统相比,可以在显著缩短的时间内对高速存储器进行评估和测试。
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