A probabilistic and timed verification approach of SysML state machine diagram

Abdelhakim Baouya, Djamal Bennouar, O. Mohamed, Samir Ouchani
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引用次数: 9

Abstract

Timed-constrained and probabilistic verification approaches gain a great importance in system behavior validation. They enable the evaluation of system behavior according to the design requirements and ensure their correctness before any implementation. In this paper, we propose a probabilistic and timed verification framework of State Machine diagrams extended with time and probability features. The approach consists on mapping the extended State Machine diagram to its equivalent probabilistic timed automata that is expressed in PRISM language. To check the functional correctness of the system under test, the properties are expressed in PCTL temporal logic. We demonstrate the approach efficiency by analyzing performability properties on a Automatic Teller Machine (ATM) case study.
一种SysML状态机图的概率和时间验证方法
时间约束和概率验证方法在系统行为验证中占有重要地位。它们能够根据设计需求对系统行为进行评估,并在任何实现之前确保其正确性。本文提出了一种扩展了时间和概率特征的状态机图的概率和时间验证框架。该方法包括将扩展状态机图映射到用PRISM语言表示的等效概率时间自动机。为了检查被测系统的功能正确性,属性用PCTL时态逻辑表示。通过分析自动柜员机(ATM)的性能特性,证明了该方法的有效性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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