{"title":"Prediction of reference spur in frequency synthesisers","authors":"Debashis Mandal, P. Mandal, T. K. Bhattacharyya","doi":"10.1049/iet-cds.2014.0019","DOIUrl":null,"url":null,"abstract":"This paper reports an analytical approach to predict the reference spur of a conventional frequency synthesiser more accurately in comparison with the existing technique where the ripple voltage waveform at voltage controlled oscillator input is approximated by narrow rectangular pulse. In this work, the ripple voltage waveform is represented by a combination of triangular and rectangular pulses. Transistor level SPICE simulations show that using the proposed approach, the error in the predicted spur has been reduced from about 29.84 to 0.64 dB. Measured result shows 4.39 dB error in the predicted spur. The derived expression has been extended further to predict the spur in frequency synthesisers having pulse repetition-based spur reducing technique including the repetition mismatch.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2015-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IET Circuits Devices Syst.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1049/iet-cds.2014.0019","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
This paper reports an analytical approach to predict the reference spur of a conventional frequency synthesiser more accurately in comparison with the existing technique where the ripple voltage waveform at voltage controlled oscillator input is approximated by narrow rectangular pulse. In this work, the ripple voltage waveform is represented by a combination of triangular and rectangular pulses. Transistor level SPICE simulations show that using the proposed approach, the error in the predicted spur has been reduced from about 29.84 to 0.64 dB. Measured result shows 4.39 dB error in the predicted spur. The derived expression has been extended further to predict the spur in frequency synthesisers having pulse repetition-based spur reducing technique including the repetition mismatch.