Design of a 50 Gbit/s InP/InGaAs HBT master-slave D-type flip-flop

Abstract

The design of a 50 Gbit/s master-slave D-type flip-flop for ETDM transmission system is presented. The chip is fabricated in an InP/InGaAs DHBT self-aligned technology with typical Ft and Fmax of about 160 GHz and 210 GHz respectively. We show how our design benefits at best from the available technology. The switching of the transistors is optimised as well as the sizing of basic blocks like emitter-followers or current switches. At this operating frequency, the layout step imposes to take into account propagation phenomena and interconnection parasitic elements, which necessarily degrade the performances. Appropriate methods are systematically applied to evaluate and reduce these effects.