A Low Power, Low Chip Area, Two-stage Current-mode DAC Implemented in CMOS 130 nm Technology

2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems" Pub Date : 2019-06-01 DOI:10.23919/MIXDES.2019.8787079

J. Dalecki, R. Dlugosz, T. Talaśka, G. Fischer

{"title":"A Low Power, Low Chip Area, Two-stage Current-mode DAC Implemented in CMOS 130 nm Technology","authors":"J. Dalecki, R. Dlugosz, T. Talaśka, G. Fischer","doi":"10.23919/MIXDES.2019.8787079","DOIUrl":null,"url":null,"abstract":"The paper presents measurement results of a current mode digital-to-analog converter (DAC), implemented in the IHP CMOS 130 nm technology. The proposed two-stage DAC is composed of 10 branches, so theoretically 10 bits of the resolution may be obtained. The circuit is reconfigurable. This means that if smaller resolutions are sufficient, the user may select the branches that are used in data conversion. The measurements were carried-out using a programmable measurement setup, designed for this purpose, equipped with precise current sources. Five samples of the prototype chip were tested. The measurements were carried out for different values of particular parameters. The circuit has been designed as one of the components of a Successive Approximation Register (SAR) analog-to-digital converter (ADC). However, it can be used as a separate block also for other purposes. The chip area of the overall ADC does not exceed 0.01 mm2, with the DAC occupying 60 % of this area.","PeriodicalId":309822,"journal":{"name":"2019 MIXDES - 26th International Conference \"Mixed Design of Integrated Circuits and Systems\"","volume":"117 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 MIXDES - 26th International Conference \"Mixed Design of Integrated Circuits and Systems\"","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/MIXDES.2019.8787079","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

Abstract

The paper presents measurement results of a current mode digital-to-analog converter (DAC), implemented in the IHP CMOS 130 nm technology. The proposed two-stage DAC is composed of 10 branches, so theoretically 10 bits of the resolution may be obtained. The circuit is reconfigurable. This means that if smaller resolutions are sufficient, the user may select the branches that are used in data conversion. The measurements were carried-out using a programmable measurement setup, designed for this purpose, equipped with precise current sources. Five samples of the prototype chip were tested. The measurements were carried out for different values of particular parameters. The circuit has been designed as one of the components of a Successive Approximation Register (SAR) analog-to-digital converter (ADC). However, it can be used as a separate block also for other purposes. The chip area of the overall ADC does not exceed 0.01 mm2, with the DAC occupying 60 % of this area.

查看原文本刊更多论文

一种采用CMOS 130纳米技术实现的低功耗、低片面积、两级电流模DAC

本文介绍了一种采用IHP CMOS 130纳米技术实现的电流模数模转换器(DAC)的测量结果。所提出的两级DAC由10个支路组成，因此理论上可以获得10位的分辨率。电路是可重构的。这意味着如果较小的分辨率就足够了，用户可以选择在数据转换中使用的分支。测量是使用可编程的测量装置进行的，为此目的而设计，配备了精确的电流源。对原型芯片的5个样品进行了测试。对特定参数的不同值进行了测量。该电路被设计为逐次逼近寄存器(SAR)模数转换器(ADC)的组成部分之一。然而，它也可以作为一个单独的块用于其他目的。整个ADC的芯片面积不超过0.01 mm2，其中DAC占该面积的60%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems"

自引率

0.00%

发文量