Optimization and scaling of an SOI TFET with back gate control

Abstract

A hetero gate dielectric SOI TFET is presented here. The device performance is observed in TCAD. The effect of channel doping on the device characteristics is studied. Moreover, the effect of different gate dielectrics on the ON current, OFF current, band-to-band generation rate due to different body layer thickness, and variation of oxide thickness effect on ON and OFF currents are observed. The variation of transfer characteristics, band-to-band generation rate for various back gate voltages are also observed. In comparison with the conventional TFET, the proposed device provides higher ON state current and a better ON state to OFF state current ratio and Subtheshold Swing. Moreover, the Tunnel FET ON state is independent of back gate voltage, only the subthreshold region is varying with back gate voltage unlike MOSFET.