Single-chip FEC codec LSI using iterative CSOC decoder for 10 Gb/s long-haul optical transmission systems

K. Seki, Kousuke Mikami, M. Baba, A. Katayama, H. Tanaka, Y. Hara, M. Kobayashi, N. Okada
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引用次数: 13

Abstract

This paper describes a 10 Gb/s throughput FEC (Forward Error Correction) codec LSI for long-haul optical transmission systems. The FEC codec uses concatenated Reed-Solomon (255,239) and Convolutional Self Orthogonal Code (CSOC). In order to improve the error correction capability, the FEC code applies iterative CSOC decoding. As a result, the FEC codec provides 8.0 dB net coding gain at 1E-12 corrected bit error rate with 25% redundancy. Due to the low complexity of CSOC, the codec achieves a low power consumption of 3.59 W and a low gate count of 1.32 Mgates using 0.18 /spl mu/m CMOS technology.
采用迭代CSOC解码器的单片FEC编解码LSI用于10gb /s长途光传输系统
介绍了一种用于长距离光传输系统的10gb /s吞吐量FEC (Forward Error Correction)编解码LSI。FEC编解码器使用连接Reed-Solomon(255,239)和卷积自正交码(CSOC)。为了提高FEC码的纠错能力,采用了迭代CSOC译码。因此,FEC编解码器在1E-12校正误码率下提供8.0 dB的净编码增益,冗余率为25%。由于CSOC的低复杂度,该编解码器采用0.18 /spl mu/m CMOS技术实现了3.59 W的低功耗和1.32 Mgates的低门数。
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