An Efficient Technique for Preventing Single Event Disruptions in Synchronous and Reconfigurable Architectures

Abstract

This paper presents a unique SEU (single event upset) mitigation technique based upon temporal data sampling for synchronous circuits and configuration bit storage for programmable devices. The design technique addresses both conventional static SEUs and SETs (single event transients) induced errors that can result in data loss for any synchronous and reconfigurable architecture. The proposed scheme may be employed in circuits to eliminate all SEUs and SETs for performance critical applications.. This approach permits FPGAs and other microcircuits with deep submicron feature size to be used in hostile space environments. Results included show that the proposed scheme is approximately 55% area and 63% power efficient than previously introduced schemes