Positive envelope feedback for linearity improvement in RFIC PAs

Abstract

This paper introduces a dynamic biasing technique intended for Radio Frequency Integrated Circuit (RFIC) power amplifiers (PAs), using positive envelope feedback based on the instantaneous envelope signal at the output of the PA, for linearity improvement. Through the simulation, design and implementation of a 5.4 GHz SOI-CMOS PA, we demonstrate that the proposed positive envelope feedback technique allows extending the output 1 dB compression (P1dB) point by 1.7 dB while meeting stability and noise requirements for a PA with P1dB of 19.5 dB m. As a result, the same linearity performance is met at a higher power level, without resorting to device size increase and the associated current increase. Hence, the technique improves the efficiency/linearity trade-off. Moreover, the described technique requires negligible additional quiescent current, minimum additional chip area and has the potential for wide bandwidths, which makes it attractive for RFIC PAs.