Through Silicon Via Oxide Etch Back for Via-last Integration Scheme

Abstract

The TSV technology has become the key driver for advanced electronic packages such as 3D memory and BSI (backside illuminated image) sensor applications. Among the various methods of integrating the TSVs (via first, via middle, and via last, via after bonding), via last, or via after bonding has gained much interest. This method helps process integration by reducing the impact on the BEOL processing and does not demand a TSV reveal for wafer thinning. However, an efficient TSV's bottom oxide etch back is necessary for making contact with the underneath interconnect layer. One potential challenge in TSV etch is in protecting the top corner of TSV liner oxide during etch back for better electrical reliability. It is due to the lower etch rate at the bottom of the via compared to the TSV top corner. This work focuses on process methodology to increase the bottom oxide etch rate with reduced TSV top corner oxide etch rate. The oxide etch back process has been optimized with a fluorine-deficient regime to minimize the etch rate difference. The optimized process suggests that - adding a slight amount of O2 with Ar-diluted C4F8 plasma helps protect the top corner oxide by depositing a passivation layer.