Optimization techniques of on-chip memory system based on UltraSPARC architecture

Abstract

It is of great significance to optimize the design of on-chip memory system for improving the performance of multi-core processor. This paper describes the organization of on-chip memory hierarchy in UltraSPARC T2, analyzes the procedure of dealing with the memory access request from multi-core processor in detail. To get the basic parameters of timing characteristic and area consumption, the primary element of on-chip memory system is simulated by ModelSim and synthesized by Synopsys Design Complier with 90nm standard cell library. Aimed at the potential limiting factor of improving the performance of memory hierarchy, corresponding optimization techniques of critical elements in memory system are explored finally.