Scalable and Memory-Efficient Spin Locks for Embedded Tile-Based Many-Core Architectures

Abstract

Embedded many-core System-on-Chip (SoC) architectures require scalability and memory constraints. However, communication between many cores, especially locking mechanisms of operating systems, is often the main obstacle to scalable and memory-efficient processing. Existing scalable spin locks consume non-negligible amounts of memory in many-core architectures, thus they are not suitable for memory constrained systems. This paper focuses on a combination of a global Mellor-Crummey and Scott (MCS) queue lock, and local ticket (TKT) locks. We refer to this lock as the C-MCS-TKT lock, which has much better memory efficiency than other scalable spin locks without degrading scalability. In addition, this paper also presents a memory-optimized version of the C-MCS-TKT lock, which slightly degrades scalability but reduces memory fragmentation, compared to the original C-MCS-TKT lock. Experimental results show that these locks have comparable performance to those of other highly scalable spin locks.