Power Amplifier Design Optimized for Envelope Tracking

Abstract

In this paper, we present the design of an inverse Class F power amplifier GaN MMIC, specifically designed for an envelope-tracking application. Power transistors are not typically characterized for the drain modulation that is fundamental to envelope tracking, and the available device models are not usually validated over the required drain bias range. Here, we used fundamental load-pull to characterize a 6×100μm GaN HEMT device over the range of drain bias voltages that would be used in the envelope-tracking PA. This data was scaled to an 8×100μm device to achieve the target output power, and these empirical load-pull models were then used in the design of the power MMIC along with harmonic design in simulation. A total of eight 8×100 μm HEMTs were used in the final design, achieving a maximum power output of 32 W at 10 GHz with a drain efficiency of greater than 45% in back-off, on a die size of less than 4 × 4 mm2 under envelope tracking.