Optimized embedded memory diagnosis

M. D. Carvalho, P. Bernardi, M. Reorda, Nicola Campanelli, T. Kerekes, D. Appello, M. Barone, V. Tancorre, Marco Terzi
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引用次数: 9

Abstract

This paper describes an optimized embedded memory diagnosis flow that exploits many levels of knowledge to produce accurate failure hypothesis. The proposed post-processing analysis flow is composed of many steps investigating failure shapes as well as cell fail syndromes, and includes advanced techniques to tackle incomplete data possibly due to tester noise and/or by faults showing intermittent effects. The effectiveness of the technique is demonstrated on an automotive-oriented System-on-Chip (SoC) manufactured in a 90nm technology by STMicroelectronics, which includes embedded SRAM memory cores tested using a programmable BIST. Scrambled BITMAPS gives a visual feedback leading to quick physical defect identification. Such research is relevant to aid on the manufacturing, material and process enhancements raising silicon yield.
优化的嵌入式内存诊断
本文描述了一种优化的嵌入式内存诊断流程,该流程利用多层知识生成准确的故障假设。提出的后处理分析流程由许多步骤组成,包括调查故障形状和细胞故障综合征,并包括先进的技术来处理可能由于测试仪噪声和/或故障显示间歇性影响而导致的不完整数据。该技术的有效性在意法半导体采用90nm工艺制造的面向汽车的片上系统(SoC)上得到了验证,其中包括使用可编程BIST测试的嵌入式SRAM存储器内核。打乱位图提供了一个视觉反馈,导致快速的物理缺陷识别。这些研究对提高硅产量的制造、材料和工艺改进具有重要意义。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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