Emitter Pedestal Design of GaInP/GaAs Heterojunction Bipolar Transistors

Abstract

This paper shows some consequences of the design of the emitter pedestal in the electric DC and AC performance of GalnP/GaAs Heterojunction Bipolar Transistors. Two HBT transistors are compared which have the same wafer area and base and collector contact areas, and very similar cutoff frequency and maximum frequency, approximately 80 and 40 GHz. The results show that it is possible to optimize the heterojunction bipolar transistor design keeping the MMIC rules and the wafer area utilized.