Performance Evaluation of Block-Based Adaptive Algorithms

Abstract

Performance of real-time digital signal processing systems is limited by their data computing capability. Therefore, evaluation of different architectures to determine the most efficient one is an important task. An efficient architecture for the implementation of block-based least mean square (LMS) adaptive filter is presented in this paper. In order to achieve lower adaptation delay different methods for optimization are used. Proposed solution is implemented in FPGA technology. Adaptive filters with different orders and block lengths are analyzed. Simulation results indicate that, compared to sample by sample based algorithm, the adaptation delay may be reduced by up to $N$ times, where $N$ is the block size of input data samples.