M. Schindler, S. Chu, T. Kazior, A. Bertrand, K. Simon
{"title":"A single chip 2.20 GHz T/R module","authors":"M. Schindler, S. Chu, T. Kazior, A. Bertrand, K. Simon","doi":"10.1109/MCS.1990.110948","DOIUrl":null,"url":null,"abstract":"A single-chip 2-20-GHz transmit/receive (T/R) module has been fabricated. This monolithic microwave IC (MMIC) includes a four-stage power amplifier chain, a four-stage low-noise amplifier, chain, and two T/R switches. A selective ion implantation process was used. One implant profile was optimized for low-noise operation and a second was optimized for power performance. All the circuits were designed to be relatively insensitive to process variations, thereby ensuring adequate yield despite the complexity of the chip. Distributed amplifiers are used throughout, and the T/R switches use a standard series-shunt FET configuration. All circuits have been miniaturized to keep the total chip size small. The entire T/R circuit measures only 0.143 in*0.193 in (3.6 mm*4.9 mm).<<ETX>>","PeriodicalId":388492,"journal":{"name":"IEEE Symposium on Microwave and Millimeter-Wave Monolithic Circuits","volume":"38 2","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Symposium on Microwave and Millimeter-Wave Monolithic Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MCS.1990.110948","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
A single-chip 2-20-GHz transmit/receive (T/R) module has been fabricated. This monolithic microwave IC (MMIC) includes a four-stage power amplifier chain, a four-stage low-noise amplifier, chain, and two T/R switches. A selective ion implantation process was used. One implant profile was optimized for low-noise operation and a second was optimized for power performance. All the circuits were designed to be relatively insensitive to process variations, thereby ensuring adequate yield despite the complexity of the chip. Distributed amplifiers are used throughout, and the T/R switches use a standard series-shunt FET configuration. All circuits have been miniaturized to keep the total chip size small. The entire T/R circuit measures only 0.143 in*0.193 in (3.6 mm*4.9 mm).<>