High Performance Fast Multiplier

Abstract

Binary multiplication is very crucial arithmetic operations in digital signal processing systems as well as general computer systems because the performance of the processor is significantly influenced by the speed of their multipliers. In this paper, we present a design-methodology for high-speed multiplications, where two integers of n-bit size each are multiplied to produce a 2n-bit product. This paper presents an efficient method for performing multiplications in one step from the least significant bit towards the most significant bit.