V-HOLT verifier - An automatic formal verification tool for combinational circuits

Abstract

Formal verification using theorem proving ascertains 100% accuracy of digital circuit verification and is thus far more useful than simulation. However, most of the theorem proving based formal verification tools do not accept commonly used HDLs, like VHDL or Verilog, and require their users to manually conduct the verification, which is a step that involves rigorous mathematical analysis. It is due to these limitations that theorem proving based verification tools are not commonly used in the industry despite their ultimate accuracy guarantee. As a first step to overcome these limitations, we present an automatic verification tool, V-HOLT Verifier, for the verification of combinational circuits described in VHDL format. Besides the VHDL description, the user of the tool provides the property that needs to be verified using a user friendly JAVA based interface. The verification of the property is done using the HOL4 theorem prover, which is a widely used theorem proving tool based on higher-order logic. The translation to HOL4 compatible code and the generation of HOL4 verification script is automatically done and thus the user is not involved with these details, which makes V-HOLT Verifier quite user friendly. The final outcome is in the form of ‘Goal Proved’, if the property is verified, or an ‘Error Trace’ in case the failure. For illustration purposes, we tested some commonly combinational circuits including 4 × 1 MUX and a full adder.