Effect of the resistance of open and short faults on the production testing of MCML gates

Abstract

This paper focuses on the production testing of MOS Current Mode Logic (MCML) gates based on 45nm MOS technology. The effect of the resistance value of open faults in an NAND/AND gate is investigated. It is shown that the test speed is determined by the characteristics of the pull up load. Open faults in other transistors are not affected by test speed. Also, it is proven that only three ordered test vectors are needed to detect all open as well as short resistive faults in the gate. Finally, the effect of the resistance of short faults is studied and it is found that the value of the resistance of the short does not affect the ability of vectors to detect faults in the 45nm technology while this is not the case for the 90nm MCML or the 45nm CMOS technologies.