{"title":"Ultimate single electronics with silicon nanowire MOSFETs","authors":"A. Fujiwara, K. Nishiguchi, G. Yamahata, K. Chida","doi":"10.23919/SNW.2017.8242277","DOIUrl":null,"url":null,"abstract":"Scaling of silicon MOSFETs has been predicted to go around 10 nm and below. For such a small transistor a gate-all-around nanowire is regarded as an ideal geometry to maintain gate control. On the other hand, such downsizing and excellent gate control has provided opportunities to control individual electrons one by one by placing gates on top of the nanowire to define charge islands and potential barriers electrically. In addition prominent stability and reproducibility of silicon MOSFETs are undoubted benefits for practical applications of such devices.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Silicon Nanoelectronics Workshop (SNW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/SNW.2017.8242277","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Scaling of silicon MOSFETs has been predicted to go around 10 nm and below. For such a small transistor a gate-all-around nanowire is regarded as an ideal geometry to maintain gate control. On the other hand, such downsizing and excellent gate control has provided opportunities to control individual electrons one by one by placing gates on top of the nanowire to define charge islands and potential barriers electrically. In addition prominent stability and reproducibility of silicon MOSFETs are undoubted benefits for practical applications of such devices.