Third Generation Signal Integrity Tools and Issues

Abstract

There exist two types of Signal integrity tool sets. One for the high level design of high performance packaging structures, and one for the verification of a package design after the interconnection wiring has been completed based on the rules and directions developed during the high level design. Not only the components of these tool sets are different, but also, even when the components of these tool sets are similar, their attributes are very different because of the different objectives that such components are required to fulfill. In this talk we will consider the tools used for the verification of the design of a package structure after its physical wiring has been completed. As we will show the ability to develop such tools presupposes the availability of adequate high level design signal integrity tools. This type of signal integrity tools includes accurate electrical parameter extractors for large physical structures, and accurate circuit analysis programs. It is to be noted that for this category of tools the main objective is their accuracy and ability to handle large physical structures, while their execution time is not as important for reasons that will become clear in the following. To the contrary for the verification tools the opposite is true. The development of both types of tools has started in IBM a long time ago, because of the needs of the mainframe computers that IBM has been provided to the market from the beginning of the computer age. Even the early versions of these systems required high frequency interconnections to support SMP servers ( Symmetric Multiprocessing ) that in turn required very large volumetric densities of the processor chips. These requirements resulted in the use of Multi Chip Modules (or MCM) namely, ceramic structures carrying large numbers of the Silicon chips ( either bipolar in the decade of 70s and 80s, or CMOS in the 90s ), and a large number of interconnections ranging from 5000 to 18000. In addition, the design of such complicated systems required the involvement of different skills from different engineering areas, and hence the need of comprehensive hand shakes for the progression of the package design from one phase to the next. Clearly, one of the most important phases is the delivery of the paper design of an MCM for its implementation to manufactured product. This is even more important for the ceramic MCM technology due to its long manufacturing TAT ( Turn Around Time). Therefore, the first generation of package design verification tools was developed in IBM in the 80s, in order to make sure that single pass design of MCMs could be achieved. The first generation of these tools was reflecting the technology needs and requirements but in addition, it established a set of attributes that such tools should have that transcends their particular application. In this presentation we shall describe these attributes that define the accuracy and execution time limitations, as well as the limitations that these tools had with respect to the interconnection topology considered. As the CMOS technology became the pervasive technology for all computing systems, and facilitated the significant increase of the interconnection speed and number of system components within one box, the needs of the mainframes in yesteryears became very similar to the needs for the field replaceable units of the current products.