A hybrid built-in self-test scheme for DRAMs

VLSI Design, Automation and Test(VLSI-DAT) Pub Date : 2015-04-27 DOI:10.1109/VLSI-DAT.2015.7114502

Chi-Chun Yang, Jin-Fu Li, Yun-Chao Yu, Kuan-Te Wu, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, D. Kwai, Yung-Fa Chou

引用次数: 6

Abstract

This paper proposes a hybrid BIST scheme for DRAMs. The hybrid BIST consists of a microcode-based controller to support the programmability of test algorithms and an FSM-based controller to support the in-field programmability of configuration parameters of the DRAMs. Thus, if the needed test algorithms are out of the test algorithms stored in the microcodes, only metal changing is needed to change the supported test algorithms. Simulation results show that the hybrid BIST only needs about 9553 gates to support march and non-march test algorithms for JEDEC WideIO DRAMs.

查看原文本刊更多论文

一种用于dram的混合内置自检方案

本文提出了一种用于dram的混合BIST方案。混合BIST由一个基于微码的控制器和一个基于fsm的控制器组成，前者支持测试算法的可编程性，后者支持dram配置参数的现场可编程性。因此，如果所需的测试算法不在存储在微码中的测试算法中，则只需更改金属即可更改所支持的测试算法。仿真结果表明，该混合BIST仅需要9553个栅极，即可支持JEDEC WideIO dram的行军和非行军测试算法。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

VLSI Design, Automation and Test(VLSI-DAT)

自引率

0.00%

发文量