{"title":"Unique folding and hysteresis characteristics of RTD for multi-valued logic and counting applications","authors":"Sen Jung Wei, H. Lin","doi":"10.1109/ISMVL.1992.186774","DOIUrl":null,"url":null,"abstract":"A multivalued counter and a multivalued full adder based on the resonant tunneling diode (RTD) are described. The counter takes advantage of the hysteresis I-V characteristic to increase the tolerances of the circuit. The counter can operate for a wide range of input pulse characteristics and circuit parameters. The sum output of the full adder is generated by taking advantage of the folding characteristic of multipeak RTDs. The speed of the full adder is greatly improved because of the parallel processing of the carry output and the sum output. SPICE3 simulations of a quaternary full adder show that the full adder could operate above 1 GHz. Experimental results for breadboarded circuits are presented for a three-valued counter and a ternary full adder.<<ETX>>","PeriodicalId":127091,"journal":{"name":"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.1992.186774","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
A multivalued counter and a multivalued full adder based on the resonant tunneling diode (RTD) are described. The counter takes advantage of the hysteresis I-V characteristic to increase the tolerances of the circuit. The counter can operate for a wide range of input pulse characteristics and circuit parameters. The sum output of the full adder is generated by taking advantage of the folding characteristic of multipeak RTDs. The speed of the full adder is greatly improved because of the parallel processing of the carry output and the sum output. SPICE3 simulations of a quaternary full adder show that the full adder could operate above 1 GHz. Experimental results for breadboarded circuits are presented for a three-valued counter and a ternary full adder.<>