Harnessing FPGAs for computer architecture education

Abstract

Computer architecture is often taught by having students use software to design and simulate individual pieces of a computer processor. We have developed a method that will take this classwork beyond software simulation into actual hardware implementation. Students will be able to design, implement, and run a single-cycle MIPS processor on an FPGA. This paper presents the major steps in this work: the FPGA implementation of a MIPS processor, a debugging tool which provides complete control and observability of the processor, the reduction of the MIPS instruction set into the eight instructions that will be used by the processor, and an assembler that can map any MIPS non-floating point instruction into this set of eight supported instructions.