SDC cell-a novel CMOS/BiCMOS design methodology for mainframe arithmetic module generation

Abstract

The shielded dynamic complex-gate (SDC) cell is a novel CMOS/BiCMOS cell-based design methodology for generating high-speed modules or macro-cells using precharged circuit technology. Since precharged circuits have inherent difficulties such as noise and clock distribution, cell-based design approaches using DA systems cannot be adopted. The SDC cell has been developed to solve this problem and requires as little design time as the poly-cell approach. The SDC cell has the following features: (1) noise-tolerant CMOS/BiCMOS precharged circuits; (2) a unique cell layout concept with a shielded structure; and (3) a clock distribution system design to minimize clock skew. Applications to a 32-bit ALU (arithmetic logic unit) and a mainframe execution unit (parallel adder) are also described