K. Yoshikawa, Yuji Harada, N. Miura, Noriaki Takeda, Yoshiyuki Saito, M. Nagata
{"title":"Immunity evaluation of inverter chains against RF power on power delivery network","authors":"K. Yoshikawa, Yuji Harada, N. Miura, Noriaki Takeda, Yoshiyuki Saito, M. Nagata","doi":"10.1109/EMCCOMPO.2013.6735206","DOIUrl":null,"url":null,"abstract":"Direct RF power injection on a power delivery network causes timing variations of inverter chains. The amount of period jitter in an inverter chain is strongly dominated by the frequency and amplitude of sinusoidal voltage variations on its internal power supply nodes. The conduction and conversion characteristics of the RF power from an external point of injection to the sinusoidal voltage variation on the node within a chip are modeled with a chip-package-board integrated network. The period jitter is calculated in response to the sinusoidal waveform with the voltage-dependent delay characteristics of an inverter stage. The external RF power is therefore analytically related with the period jitter of an inverter chain. Comparisons are made between the calculation and measurements for a 65 nm CMOS prototype chip featuring on-chip voltage waveform monitoring functions.","PeriodicalId":302757,"journal":{"name":"2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"411 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EMCCOMPO.2013.6735206","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
Direct RF power injection on a power delivery network causes timing variations of inverter chains. The amount of period jitter in an inverter chain is strongly dominated by the frequency and amplitude of sinusoidal voltage variations on its internal power supply nodes. The conduction and conversion characteristics of the RF power from an external point of injection to the sinusoidal voltage variation on the node within a chip are modeled with a chip-package-board integrated network. The period jitter is calculated in response to the sinusoidal waveform with the voltage-dependent delay characteristics of an inverter stage. The external RF power is therefore analytically related with the period jitter of an inverter chain. Comparisons are made between the calculation and measurements for a 65 nm CMOS prototype chip featuring on-chip voltage waveform monitoring functions.