Plasma induced damage of aggressively scaled gate dielectric (EOT ≪ 1.0nm) in metal gate/high-k dielectric CMOSFETs

K. Min, C. Kang, Ooksang Yoo, B. Park, Sung Woo Kim, C. Young, D. Heh, G. Bersuker, B. Lee, G. Yeom
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引用次数: 12

Abstract

Sample devices were fabricated with 2.0 nm SiO2 and 2.5-10.0 nm HfO2. Transistor transconductance and gate leakage were used to evaluate PID. BTI and dielectric breakdown were measured to study the PID effect. For both nMOSFETs and pMOSFETs, the transconductance was degraded for the different antenna structures. It was found that, even below 0.9 nm of EOT range, the plasma charging damage was observed for various device parameters. This plasma damage can deteriorate the reliability of sub 32 nm metal gate/high-k dielectric CMOSFETs.
金属栅极/高k介电cmosfet中栅极电介质(EOT≪1.0nm)的等离子体损伤
采用2.0 nm SiO2和2.5 ~ 10.0 nm HfO2制备样品器件。利用晶体管跨导和栅极漏电流对PID进行评价。通过测量BTI和介电击穿来研究PID效应。对于nmosfet和pmosfet,不同的天线结构会降低其跨导性。研究发现,即使在0.9 nm的EOT范围内,在不同的器件参数下也能观察到等离子体充电损伤。这种等离子体损伤会降低32nm金属栅/高k介电cmosfet的可靠性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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