Pratik P Pandit, L. Arivazhagan, P. Prajoon, J. Rajkumar, J. Ajayan, D. Nirmal
{"title":"DC Performance analysis of AlGaN/GaN HEMT for future High power applications","authors":"Pratik P Pandit, L. Arivazhagan, P. Prajoon, J. Rajkumar, J. Ajayan, D. Nirmal","doi":"10.1109/ICDCSYST.2018.8605071","DOIUrl":null,"url":null,"abstract":"In this work, we analyzed the DC performance of asymmetric AlGaN/GaN High Electron Mobility Transistors (HEMTs) on SiC substarte using Silvaco-TCAD software. The highlights of the proposed HEMT are intrinsic GaN channel, AlN nucleation layer, AIGaN barrier layer and asymmetric gate technology and GaN cap layer. The $\\mathrm {L}_{\\mathrm {g}} = 50$ nm proposed HEMT on SiC substrate exhibits a $\\mathrm {g}_{\\mathrm {m}_{-}\\max }$ of 170 mS/mm and $\\mathrm {I}_{\\mathrm {D}\\mathrm {S}_{-}\\max }$ of 800 mA/mm and breakdown voltage of 550 V. The proposed HEMT on SiC substrate exhibits a threshold voltage of -5V which indicates its D-Mode operation of the device. This excellent DC and breakdown characteristics of the proposed HEMT makes them an excellent candidate for future high power and high frequency applications.","PeriodicalId":175583,"journal":{"name":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 4th International Conference on Devices, Circuits and Systems (ICDCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICDCSYST.2018.8605071","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
In this work, we analyzed the DC performance of asymmetric AlGaN/GaN High Electron Mobility Transistors (HEMTs) on SiC substarte using Silvaco-TCAD software. The highlights of the proposed HEMT are intrinsic GaN channel, AlN nucleation layer, AIGaN barrier layer and asymmetric gate technology and GaN cap layer. The $\mathrm {L}_{\mathrm {g}} = 50$ nm proposed HEMT on SiC substrate exhibits a $\mathrm {g}_{\mathrm {m}_{-}\max }$ of 170 mS/mm and $\mathrm {I}_{\mathrm {D}\mathrm {S}_{-}\max }$ of 800 mA/mm and breakdown voltage of 550 V. The proposed HEMT on SiC substrate exhibits a threshold voltage of -5V which indicates its D-Mode operation of the device. This excellent DC and breakdown characteristics of the proposed HEMT makes them an excellent candidate for future high power and high frequency applications.