Interconnect technology for giga-scale integration

Abstract

Key interconnect issues for giga-scale integration, interconnect architecture, delay and yield, are examined. Even using new materials. Cu and low K dielectric (K=2), interconnect delay still dominates and clock speed of 2 GHz for large circuits is not achievable without new innovation in architecture. Cumulative yield loss from multiple levels of interconnect will dominate the die yield, and the more promising reverse-scaling architecture suffers more severe yield loss due to increased die size. Overall, interconnect technology, at giga-scale integration will be one of the most challenging tasks and innovation in architecture is needed.