A VLSI Architecture for Signed Multipliers

Abstract

Multipliers are basically the heart of ALU for any processor. The performance of the DSP processors depends on the computation time of the multipliers. For hardware implementation of DSP based applications, we need proper optimization of adder and multiplier architecture. Also most of the signal processing applications deal with negative data to be processed for accurate result. In this paper a signed system is designed and implemented on an unsigned Wallace-tree and Array multiplier with Vivado 2017.4. The Modified multipliers are compared with signed Booth Multiplier with respect to the data obtained before and after implementation on xc7a100tcsg324-1 board. This paper gives an idea to compute negative numbers in a multiplier and obtain better performance.