A VLSI Architecture for Signed Multipliers

Uditnarayan Mandal, Ruby Mishra
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Abstract

Multipliers are basically the heart of ALU for any processor. The performance of the DSP processors depends on the computation time of the multipliers. For hardware implementation of DSP based applications, we need proper optimization of adder and multiplier architecture. Also most of the signal processing applications deal with negative data to be processed for accurate result. In this paper a signed system is designed and implemented on an unsigned Wallace-tree and Array multiplier with Vivado 2017.4. The Modified multipliers are compared with signed Booth Multiplier with respect to the data obtained before and after implementation on xc7a100tcsg324-1 board. This paper gives an idea to compute negative numbers in a multiplier and obtain better performance.
用于符号乘法器的VLSI架构
乘法器基本上是任何处理器的ALU的核心。DSP处理器的性能取决于乘法器的计算时间。对于基于DSP的应用的硬件实现,需要对加法器和乘法器的结构进行适当的优化。此外,大多数信号处理应用都是处理负数据以获得准确的结果。本文利用Vivado 2017.4在无符号华莱士树和数组乘法器上设计并实现了一个带符号的系统。在xc7a100tcsg324-1板上实现前后的数据,将修改后的乘法器与签名的展台乘法器进行比较。本文提出了一种在乘法器中计算负数以获得更好性能的思路。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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