{"title":"A 114-126 GHz Frequency Quintupler with >36 dBc Harmonic Rejection in 0.13 μm SiGe BiCMOS","authors":"Andrea Bilato, V. Issakov, A. Bevilacqua","doi":"10.1109/BCICTS45179.2019.8972769","DOIUrl":null,"url":null,"abstract":"This work presents a D-band frequency multiplier by five that shows a harmonic rejection higher than 36 dBc, while consuming only 59 mW from a 1.8 V supply. The fifth harmonic of the 24 GHz input signal is generated by a differential pair driven in hard switching, loaded by a fourth order passive network that filters out the undesired current harmonics. The signal is further amplified by tuned cascode stages to deliver a peak output power of -3.8 dBm. The multiplier is implemented in a 0.13 μm SiGe BiCMOS technology and operates over the 114 to 126 GHz frequency range while occupying a 0.93 × 0.93mm2 silicon area.","PeriodicalId":243314,"journal":{"name":"2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BCICTS45179.2019.8972769","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This work presents a D-band frequency multiplier by five that shows a harmonic rejection higher than 36 dBc, while consuming only 59 mW from a 1.8 V supply. The fifth harmonic of the 24 GHz input signal is generated by a differential pair driven in hard switching, loaded by a fourth order passive network that filters out the undesired current harmonics. The signal is further amplified by tuned cascode stages to deliver a peak output power of -3.8 dBm. The multiplier is implemented in a 0.13 μm SiGe BiCMOS technology and operates over the 114 to 126 GHz frequency range while occupying a 0.93 × 0.93mm2 silicon area.