Detection of faulty interswitch links in 2-D mesh network-on-chips

Abstract

The network-on-chip has become an emerging research area in the fields of system on chips, embedded systems, integrated circuits design, etc. with the rapid advancement of technologies. The introduction of multi-core chips has in addition made researches in the area ever significant and is growing to facilitate high demand of bandwidth via core utilization and need of scalable interconnection fabrics. Numerous technical papers have addressed the performance evaluation but a limited attention has been paid on detection of faulty interswitch links in post manufactured network-on-chip setups. Existing works are traditional circuit based but not with respect to current aspects. Main drawbacks of these approaches are high detection time, large test data, and low scalability. In this paper we propose a novel high level detection model for interswitch links in network-on-chips. The detection process is exercised with a set of test patterns to identify faulty links. The model proposes both local and global test generation schemes. A 2-D mesh network-on-chip architecture is considered for experiment. The experimental results show that the proposed detection model outperforms with a finite test patterns set which suffices to test all interswitch links of the underlying network-on-chip.