Design of a 3-D stacked floating-point Goldschmidt divider

Abstract

In the design of 3-D stacked floating-point units, a partitioning method affects the performance and the power consumption. To realize a high-performance and low-power 3-D stacked floating point divider, this paper proposes a circuit partitioning method for the Goldschmidt divider. The proposed partitioning method equalizes the sizes of silicon layers and reduces the number of vertical interconnects. Experimental results show the 3-D stacked Goldschmidt divider which is designed based on the proposed partitioning method achieves an 8.1% critical path delay reduction and a 6.8% average power reduction compared to the 2-D implementation.