A Platform for Monolithic Back End of Line III-V Integration

Abstract

Heterogeneous integration of high-quality crystalline semiconductor materials and devices compatible with the back end of line (BEOL) CMOS wafers are fundamentally limited by two factors: (i) the lack of a crystalline growth surface and (ii) the <400 ° C thermal budget. Here, we demonstrate a platform for monolithic integration III-V devices directly on amorphous substrates at a growth temperature of 300 ° C by low temperature templated liquid phase (LT-TLP) method. Furthermore, we demonstrate that degenerately doped materials can also be directly grown at <400 °C via LT-TLP, establishing the building blocks for high performance back end devices.