Platform PI-PD co-design and validation for power efficient HSIO interfaces

2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) Pub Date : 2017-10-01 DOI:10.1109/EPEPS.2017.8329703

X. Cai, S. G. Pang, J. Huang, Yan Li, S. Ji

引用次数: 1

Abstract

An efficient and effective methodology for platform power delivery and power integrity (PD-PI) co-analysis and design optimization has been developed, for investigating high yield loss, to support SoC validation. Both frequency and time domain results have demonstrated good correlation between simulation and lab measurement. Consequently it enabled quick verifying the root cause and optimizing work-around power delivery fixing solutions, and further provided optimal PD configuration scheme to key customers for their platform design.

查看原文本刊更多论文

低功耗HSIO接口的平台PI-PD协同设计与验证

开发了一种高效的平台功率传输和功率完整性(PD-PI)协同分析和设计优化方法，用于研究高成品率损耗，以支持SoC验证。频域和时域结果均表明仿真结果与实验室测量结果具有良好的相关性。因此，它可以快速验证根本原因并优化解决方案，并进一步为关键客户的平台设计提供最佳的PD配置方案。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)

自引率

0.00%

发文量