{"title":"Identification of power hungry unit in a processor with faulty predictor","authors":"B. Das, B. Sen, D. Saran, B. Sikdar","doi":"10.1109/ICCIRCUITSANDSYSTEMS.2012.6408318","DOIUrl":null,"url":null,"abstract":"This work reports identification of processor modules that are power hungry even for a minor defect in the branch predictor. The probable defects/faults in a predictor, resulting in mis-speculations, have been introduced to estimate the power consumption at different processor modules. The analysis reported in this work points to the power catastrophic defects that cause huge power drainage from the modules/units. Identification of such power hungry units of a processor establishes the need of DPL (design avoiding power loss) to save power drainage from a processor.","PeriodicalId":325846,"journal":{"name":"2012 IEEE International Conference on Circuits and Systems (ICCAS)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE International Conference on Circuits and Systems (ICCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCIRCUITSANDSYSTEMS.2012.6408318","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This work reports identification of processor modules that are power hungry even for a minor defect in the branch predictor. The probable defects/faults in a predictor, resulting in mis-speculations, have been introduced to estimate the power consumption at different processor modules. The analysis reported in this work points to the power catastrophic defects that cause huge power drainage from the modules/units. Identification of such power hungry units of a processor establishes the need of DPL (design avoiding power loss) to save power drainage from a processor.