{"title":"Associative memory with fully parallel nearest-manhattan-distance search for low-power real-time single-chip applications","authors":"Yuji Yano, T. Koide, H. Mattausch","doi":"10.1109/ASPDAC.2004.1337640","DOIUrl":null,"url":null,"abstract":"A fully-paralled minimum Manhattan-distance search associative memory has been designed in 0.35μm CMOS with 3-metal layers. The nearest-match unit consumes only 1.02mm2, while the chip area is 7.49mm2. The measured winner-search time of this chip, the time to determine the best-matching reference-data word for an input-data word among a database of 128 reference words (5-bit, 16 units), is < 180nsec. This corresponds to a performance requirement of 16 GOPS/mm2, if a 32-bit computer with the same chip area would have to run the same workload. Furthermore the power dissipation of the designed test chip is only about 26.7mW/mm2.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASPDAC.2004.1337640","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 14
Abstract
A fully-paralled minimum Manhattan-distance search associative memory has been designed in 0.35μm CMOS with 3-metal layers. The nearest-match unit consumes only 1.02mm2, while the chip area is 7.49mm2. The measured winner-search time of this chip, the time to determine the best-matching reference-data word for an input-data word among a database of 128 reference words (5-bit, 16 units), is < 180nsec. This corresponds to a performance requirement of 16 GOPS/mm2, if a 32-bit computer with the same chip area would have to run the same workload. Furthermore the power dissipation of the designed test chip is only about 26.7mW/mm2.