Designed & Comparison of Reliability Analysis in 6T & 5T SRAM Cell

Abstract

Temporary reduction VLSI IC silicon technology is an important factor for the scale of reliability problems. The instability of the Negative Bias Temperature Instability (NBTI), Positive Bias Temperature Instability (PBTI), Hot-Carrier Injection (HCI) and different Models are particularly severe problem during operation of the electronic circuit. This document describes the impact mechanism and another NBTI, PBTI& HCI distribution coefficient that degrades NBTI, PBTI & HCI performance. The expression analysis of the Reliability models is based on various characteristics of the solution spread of the model developed by the researcher. For NBTI, PBTI, HCI and Models performance of 6T and 5T SRAM, this method can be used to counteract the effect of PMOS NBTI degradation, NMOS PBTI degradation and HCI on both which is described in more detail below.. Certain manufacturing processes can cause destruction inactivity leading to short circuit life. In research for NBTI PBTI and HCI degradation on 6T and 5T SRAM, the draft strategy provides the effect of improving the performance of 6T and 5T SRAM. This 6T and 5T SRAM is subject to temperature and pressure stress conditions, in particular degradation appears in the device parameters. In this paper we found the degradation of 6T and 5T SRAM up to 10 years and compared the results to find effectiveness in both SRAM’s. The simulation work is done using 45nm technology in virtuoso cadence.