Subthreshold passive RFID tag's baseband processor core design with custom modules and cells

Abstract

Subthreshold ultra-low-power passive RFID tag's baseband processor core design with custom logic cells is presented in this paper, based on EPC C1G2 protocol. To deal with the critical timing and wide-range-PVT variation problems of the processor at very low power supply, and for the consideration of limited availability of RF power, power-aware ideas are applied to the processor, including data link portions. Importantly, a novel custom ratioed logic style is adopted in key modules to fundamentally solve the speed problem at ultra-low-voltage. The proposed baseband processor was fabricated in 90 nm CMOS as well as the regular design with the same function. In measurement the proposed design indicates good robustness and much more competent for subthreshold operation. It can operate at minimum 0.28 V supply with power consumption of 129 nW.