Planar gain cell for low voltage operation and gigabit memories

Abstract

A dynamic gain memory cell has been fabricated which, despite its planar design, can compete with the area requirements of one transistor DRAM cells (1T-cells) built in trench or 3D stacked technology. The described gain cell can be geometrically shrunk because the drain current of scaled down MOS transistors increases resulting in higher signal charge. Another attractive feature of the proposed gain memory cell is that it can be fabricated using a CMOS logic process to bridge the gap between DRAM and CMOS logic technology. Because of its inherent amplification, the gain cell delivers even at supply voltages below 2 V sufficient signal charge making it suitable for low voltage applications.