A Unique Design of Hybrid Full Adder for the Application of Low Power VLSI Circuits

Abstract

In this research work, a unique Hybrid Full Adder (HFA) is developed by deploying Pass Transistor Logic (PTL), CMOS logic and transmission gate (TG) logic on the Cadence Virtuoso platform in 90-nm technology. Various modules, namely the XOR module, the carry generator module, sum generator module are implemented for realizing 1-bit HFA. An inverter logic is employed next to the XOR logic to obtain the logic of XNOR which is required for designing the proposed HFA. The propagation delay (tpd) and average power of the circuit are turned out to be 20 ns and ~6.889 μW respectively, at 1V supply voltage. So, the power delay product (PDP) is remarkably low with the value 137.78 fJ of the proposed HFA. The area is also satisfyingly less because the proposed design used only 13 transistors. Hence, the proposed design gives a remarkable improvement in terms of PDP which may be applicable for basic building blocks of VLSI circuits.