A methodology to assess the influence of Burn In related to long-term reliability of submicron CMOS transistors

Abstract

We have found a suitable methodology to establish the influence of Burn In (BI) stress on transistor lifetime with respect to decreasing transistor channel lengths and simultaneously increasing energy of accelerated electrons by higher electric fields during BI. This paper describes the details of the measurement method and a transformation model, which allows us to calculate the BI influence on transistor lifetime based on standard hot carrier stress (HCS) investigations. The new method results in a considerable reduction of measurement time and a suitable way to assess the transistor lifetime reduction due to the BI procedure.