Low power SRAM design using independent gate FinFET at 30nm technology

Abstract

Energy efficient and low power circuit designing has become challenging for many years. Now a day in Modern 1C designing, SRAM design somewhat significant because it will occupy more space on a die and consumes large fraction of energy of the chip. Scaling of conventional CMOS circuit leads to have short channel effects due to which, effect such as drain induced barrier lowering, hot electron effect, punch through etc. takes place and hence leakage power increases in the transistor. In this paper, to minimize short channel effects, we have designed SRAM cell using double gate FinFET. FinFET may be the most promising device in the LSI (large scale integration) circuits because it realizes the self-aligned double-gate structure easily. Simulation is performed with Cadence virtuoso tool. The low power in SRAM is achieved by driving the two gates of FinFET independently. We have designed some SRAM circuits using FinFET and compared their results. After that, using the best configuration we have designed 8×8 memory array.